As manufacturing technology of semiconductor devices develops, an ability to highly integrate semiconductor devices may become more advanced. As a degree of integration of semiconductor devices increases, there may be an interest in miniaturizing various components.
Moreover, as semiconductor devices become more highly integrated, a wiring line width of a gate electrode or bit lines of a metal oxide semiconductor field effect transistor (referred to as ‘MOSFET’ hereinafter) may be reduced.
FIGS. 1A through 1D are example cross-sectional diagrams illustrating a related art process for manufacturing a MOSFET, including forming a gate insulating layer before forming a gate electrode.
Referring to FIGS. 1A through 1D, a gate insulating layer of a logic device may be designed to be divided into an input/output (I/O) power source wiring region and a core power source wiring region. These regions may have different thicknesses corresponding to an operating voltage.
Referring to FIG. 1A, a device isolation process may be performed for a silicon substrate, which may be semiconductor substrate 100, and may form device isolation layer 102. Device isolation layer 102 may be divided into a device active region and a device isolation region. Next, ions may be implanted in a surface of substrate 100 to form a well and to grow first oxide layer 104 as a gate insulating layer.
Referring to FIG. 1B, oxide layer 104 of the core power source wiring region may be removed by masking the I/O power source wiring region, for example through a wet etching method.
Referring to FIG. 1C, second oxide layer 106, which may have a thin/low thickness may be grown, and may be provided on the core power source wiring region.
Referring to FIG. 1D, nitrogen annealing may be performed to form a NO gate in which nitrogen-rich oxide layer 108 may be formed at an interface of the device active region.
An N trapping may occur at an interface between dual layers in the I/O power source wiring region. The greater a thickness of first oxide layer 104, the higher an occurrence rate of the trapping may be. Because of this, Si—N binding may be insufficiently formed to reduce an interface stress reduction performance, which may lead to an electric degradation.
Thereafter, doped polysilicon may be deposited as a conductive layer and a gate electrode may be formed by patterning and etching processes. A MOSFET may be completed through a series of processes, which may form lightly doped drain (LDD) regions, spacers, and source/drain (S/D).
In the related art MOSFET, because of a fineness of a semiconductor line width, so as to embody a core power source wiring region of high performance, it may be necessary to reduce a threshold voltage and a leakage occurrence due to a short channel effect.
To precisely control an LDD profile, an applied boundary of a thermal process using a furnace may be gradually limited.
In contrast to this, although a formation of an LDD profile of a graded junction structure may be necessary in the I/O power source wiring region to improve hot-carrier characteristics, as mentioned above, due to a possibility for characteristic degradation in the core power source wiring region, it may be difficult to embody an extension type LDD having a sufficient thermal energy.
In the related art, second oxide layer 106 may grow to a lower portion of first oxide layer 104 and may form a thick oxide layer over the input/output power source wiring region.
To secure excellent hot carrier injection (HCI) or negative bias temperature instability (NBTI) characteristics, it may be necessary to increase a thickness of a gate insulating layer in the I/O power source wiring region. However, when a thickness of the gate insulating layer is increased greater than a threshold value, an interface segregation of ions implanted in the lower channel region may be caused due to a stress in an interface of the device active region. This may change certain characteristics of a transistor. In a serious case, an active region of the device may be cracked.